Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a delay locked loop and an integrated circuit including the same.
In general, circuit elements such as a double data rate synchronous dynamic random access memory (DDR SDRAM) are designed to transfer data and various signals to external devices by using an internal clock synchronized with an external clock used in an external system. Here, the internal clock is synchronized with the external clock when it is initially applied to the circuit elements, but the internal clock may be delayed while passing through various elements included in the circuit elements. As a result, the internal clock is often not synchronized with the external clock when finally outputted to external devices.
In order to stably transfer the data and the various signals output from the circuit elements, the internal clock, which is delayed while passing through elements of the memory device, is to be synchronized so as to match an edge or center of the external clock applied from the external devices. More specifically, the internal clock may be synchronized with the external clock by compensating time for loading data on a bus. Examples of a clock synchronization circuit for performing the compensation of the data load time include a delay locked loop (DLL) circuit.
FIG. 1 is a block diagram of an integrated circuit including a conventional DLL.
Referring to FIG. 1, the conventional DLL includes a delay unit 101, a delay amount control unit 103, and a replica delay 105. Here, an integrated circuit comprises the conventional DLL, and first and second clock paths 107 and 109. The integrated circuit may be a single chip performing a preset function within a system, such as a dynamic random access memory (DRAM), or an entire circuit comprising a plurality of chips. In FIG. 1, each block has a delay amount when a clock passes through the component, where the delay amount is indicated by a label within a parenthesis.
The first clock path 107 is a clock path where an external clock EXTCLK, which is inputted from outside of the integrated circuit, is transmitted as an input clock INCLK of the DLL.
The second clock path 109 is a clock path where an output clock OUTCLK of the DLL is transmitted as a target clock TGCLK, which may be used in a target circuit of a system. For example, when the system is a DRAM, the target circuit may be a data pad DQ, and the target clock TGCLK may be a data strobe signal DQS for the DQ pad. In such a case, the second clock path 109 becomes a clock path where the output clock OUTCLK of the DLL is transmitted as the data strobe signal DQS to outside of the DRAM.
The delay unit 101 outputs the output clock OUTCLK by delaying the input clock INCLK by a delay amount (A).
The replica delay unit 105 outputs a feedback clock FBCLK by reflecting/applying a modeled delay amount (D1+D2) in/to the output clock OUTCLK outputted from the delay unit 101. The modeled delay amount (D1+D2) is generated by modeling a combined delay amount of a first delay amount (D1) of the first clock path 107 and a second delay amount (D2) of the second clock path 109.
The delay amount control unit 103 controls the delay amount (A) of the delay unit 101 by detecting a phase difference between the input clock INCLK and the feedback clock FBCLK.
FIG. 2 is a clock timing diagram illustrating an operation of the DLL of FIG. 1.
Referring to FIG. 2, the delay amount control unit 103 controls the delay amount (A) of the delay unit 101 to be the difference between the modeled delay amount (D1+D2) of the replica delay unit 105 and a period tCK of the input clock INCLK. Thus, a phase of the input clock INCLK may be synchronized with the phase of the feedback clock FBCLK by controlling the delay amount (A) of the delay unit 101 to be tCK−(D1+D2).
When a frequency of the input clock INCLK is higher, the modeled delay amount (D1+D2) of the replica delay unit 105 becomes greater than the period tCK of the input clock INCLK. In this case, the delay amount control unit 103 may control the input clock INCLK to be synchronized with the feedback clock FBCLK for the phase of the input clock INCLK received after lapse of several periods of the input clock as received by the delay unit 101. Accordingly, the delay amount control unit 103 controls the delay amount (A) of the delay unit 101 to equal a difference between the modeled delay amount (D1+D2) of the replica delay unit 105 and a time equal to a multiple periods tCKs of the input clock INCLK, i.e., N*tCK−(D1+D2), N being a positive integer number.
FIG. 3 is a block diagram of an integrated circuit including a conventional DLL that illustrates a method for increasing a delay amount during a low frequency operation, and FIG. 4 is a clock timing diagram illustrating the low frequency operation of the DLL of FIG. 3.
As a frequency of the input clock INCLK becomes lower, the period tCK of the input clock INCLK becomes longer. When the period tCK is longer than the modeled delay amount (D1+D2) of the replica delay unit 105 and the maximum delay amount (A) of the delay unit 101, the delay unit 101 must have an increased delay amount (B) in addition to the delay amount (A). As a result, the delay unit 101 has a delay amount (A+B) as shown in FIGS. 3 and 4.
Here, the delay unit 101 of the conventional DLL is often composed of a plurality of delay cells, each having an extremely fine unit delay amount. When the delay amount of the delay unit 101 is to be increased for a low frequency operation, an accompanying area of semiconductor circuit also increases. Also, current consumption increases and cause jitters since a clock path of the DLL becomes longer.